Circuit Compilation & Qubit Mapping
Why the circuit you design and the circuit that actually runs on a chip aren't the same circuit
By the end of this topic you'll be able to
Every circuit in this curriculum's earlier tracks was drawn assuming any two qubits could interact directly through a gate like CNOT, wherever they happened to sit in the register. Real hardware doesn't work this way: physical qubits sit on a chip with a fixed connectivity graph, often a 2D grid or something sparser, and a two-qubit gate typically only works directly between qubits that are physically adjacent.
Turning an abstract circuit into one that only uses adjacent-qubit gates is the job of a compiler, and it has two closely related tasks: mapping, choosing which physical qubit stands in for each logical qubit, and routing, inserting extra gates — typically SWAPs — to move quantum information across the chip whenever the circuit needs an interaction between qubits that aren't adjacent under the current mapping.
Every inserted SWAP is itself built from three CNOTs, and each of those CNOTs is another opportunity for the physical error described in the Noise & Error Correction track to strike. A poorly chosen mapping can multiply a circuit's effective gate count and error rate many times over compared to a well-chosen one, even though both compile the exact same logical circuit.
A further complication, absent from the earlier idealized picture, is that real qubits and gates are not uniform: on a given chip, some qubits have measurably longer T1/T2 coherence times than others, and some physical gate pairs have higher fidelity than others — often varying from one calibration cycle to the next.
Murali et al.'s 2019 paper on noise-adaptive compiler mappings makes exactly this point concrete: rather than treating every qubit and connection as interchangeable, a compiler that consults a chip's actual, continuously updated calibration data — which specific qubits and gate pairs are currently most reliable — to choose mappings and routes can substantially outperform one that only respects the abstract connectivity graph.
Their reported result illustrates how much this matters in the NISQ era covered in the previous topic: noise-aware mapping and routing improved program success rates by up to 18 times over standard compilation on real IBM hardware of the day, without changing the underlying quantum algorithm at all — the entire gain came from smarter compilation.
This remains a genuinely active research area, not a solved problem: as chips grow larger and connectivity patterns more elaborate, finding good mappings efficiently is itself a hard combinatorial optimization problem, and better noise-aware compilers are one of the most direct near-term ways to extract more useful computation from existing noisy hardware without waiting for better qubits.
It's worth connecting this back to the Software track: when a circuit built in Qiskit, Cirq, or any other SDK is submitted to real hardware, a compiler pass exactly like this runs automatically before the circuit reaches the chip. The code written and the sequence of physical pulses actually executed are, in a very concrete sense, two different circuits, related by exactly this mapping and routing process.
Try It Yourself
A chip has 4 qubits wired in a line: 0—1—2—3 (each qubit only adjacent to its immediate neighbors). A circuit needs a CNOT between qubit 0 and qubit 3. How many SWAPs are needed to bring them adjacent, and how many total CNOTs does that cost compared to running the gate directly?
- 1On this linear chain, qubit 0 and qubit 3 are 3 hops apart (0 to 1 to 2 to 3), not adjacent.
- 2To make them adjacent, move qubit 0's information two steps closer: SWAP(0,1), then SWAP(1,2) — after these two SWAPs, the information that started at qubit 0 now sits at qubit 2, directly adjacent to qubit 3.
- 3That's 2 SWAPs, and since each SWAP costs 3 CNOTs, that's 2 × 3 = 6 extra CNOTs.
- 4Add the 1 CNOT actually needed for the original gate: 6 + 1 = 7 CNOTs total, compared to just 1 CNOT if qubits 0 and 3 had been directly connected.
2 SWAPs are needed, costing 6 extra CNOTs — for a total of 7 CNOTs instead of 1, a 7× blowup purely from the chip's limited connectivity, with no change to the logical circuit at all.
Reference
| Mapping | Assigns each circuit qubit to a physical qubit on the chip | |
| Routing | Moves information between non-adjacent qubits so two-qubit gates become local | |
| SWAP cost | Each inserted SWAP adds three further opportunities for error | |
| Noise-aware gain | Reported program success-rate improvement (Murali et al., 2019) |
Quick Check
Why can't a two-qubit gate like CNOT always be applied directly between any two qubits in a circuit, on real hardware?
What does 'noise-aware' compilation add beyond just satisfying a chip's connectivity constraints?